Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - image vhdl

Search list

[VHDL-FPGA-Verilog] vgaout

Description: VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
Platform: | Size: 7168 | Author: 余飞 | Hits:

[2D Graphic] XLIB

Description: 2D图像滤波VHDL代码。 2D图像滤波VHDL代码。-2D image filtering VHDL code. 2D image filtering VHDL code. 2D image filtering VHDL code.
Platform: | Size: 13312 | Author: leisuee | Hits:

[Picture Viewer] manticore

Description: 显卡中关于3D图形处理的源码，是VHDL版本的 喜欢硬件FPGA图像处理的可以看看，挺有意思-Graphics 3D graphics on the source, is like VHDL version of the FPGA hardware image processing can see quite interesting
Platform: | Size: 1686528 | Author: dido wang | Hits:

[VHDL-FPGA-Verilog] imageEnhancement_VHDL

Description: VHDL 实现的图像增强，利用对比度增强的方法，实用-VHDL of image enhancement, use of contrast enhancement methods, practical
Platform: | Size: 115712 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] shipingkonzhi

Description: 用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,
Platform: | Size: 431104 | Author: 张龙 | Hits:

[Other Embeded program] edge_detector

Description: 基于cpld的数字图像边缘检测算法的实现，vhdl源程序-CPLD-based digital image edge detection algorithm, vhdl source code
Platform: | Size: 1024 | Author: jjaai | Hits:

[Graph Recognize] saa7113shipincaiji

Description: 视频图像采集verilog HDl源程序，视频解码芯片部分的，可以供参考-Video image acquisition verilog HDl source, part of the video decoder chip, you can for reference
Platform: | Size: 8192 | Author: 穆垚 | Hits:

[VHDL-FPGA-Verilog] color_converter.tar

Description: 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助-This code different image color conversion between formats, such as XYZ <-> RGB, different standards of RGB <-> RGB and RGB <-> YCbCr conversion between packet contains code m file matlab simulation, VHDL code . v documents and ModelSim Simulation Testbench documentation, I believe everyone will certainly help
Platform: | Size: 339968 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] vedio

Description: VHDL设计的高速图像采集模块源码，离散余弦变换，图像压缩与编码源码-VHDL design of high-speed image acquisition module source, discrete cosine transform, image compression and encoding source
Platform: | Size: 4096 | Author: | Hits:

[Software Engineering] SOC_CCD

Description: 基于SOC的线阵CCD图像采集单元设计.pdf-SOC based on the linear array CCD image acquisition unit design. Pdf
Platform: | Size: 506880 | Author: 王剑雨 | Hits:

[Special Effects] the.implement.of.image.pretreatment.algorithm.in.t

Description: 现场可编程逻辑门阵列在实时数字图像处理中的应用-Field-programmable gate array logic in real-time digital image processing
Platform: | Size: 159744 | Author: 刘文娟 | Hits:

[VHDL-FPGA-Verilog] ImageProcessing

Description: 这个是国外大学的项目代码 ，这个是数字图像处理的模块-This is a project abroad, the University of code, this is a digital image processing module
Platform: | Size: 15399936 | Author: 陈晓 | Hits:

[Wavelet] compressVLSI

Description: 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-High-speed image compression encoder the structural design of VLSI Research. Kdh quite the level of doctoral dissertation. Which describes in detail how to design the structure of wavelet transform VLSI. Verilog hdl design and structure of the assessment
Platform: | Size: 1733632 | Author: 黄辉 | Hits:

[VHDL-FPGA-Verilog] fpgajpeg

Description: 基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
Platform: | Size: 103424 | Author: 倪德 | Hits:

[VHDL-FPGA-Verilog] FPGAbi_ioreseach

Description: :针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给 出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片 设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.
Platform: | Size: 115712 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] 2DImageFilterByVHDL

Description: 用VHDL语言编程实现2维图像的滤波算法，简单精辟-VHDL programming language used to achieve 2-D image filtering algorithm, simple brilliant
Platform: | Size: 13312 | Author: 宋雪兵 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Software Engineering] Digital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[VHDL-FPGA-Verilog] filter

Description: 图像处理技术中3*3模板的滤波电路的VHDL实现.-Image processing technology in the 3* 3 template VHDL implementation of the filter circuit.
Platform: | Size: 292864 | Author: 翁文天 | Hits:

[Compress-Decompress algrithms] buffer_img

Description: buffer image coefficents for jpeg compression
Platform: | Size: 1024 | Author: sandeep | Hits:
« 12 3 4 5 6 7 8 9 10 »

CodeBus www.codebus.net